1. Field of the Invention
The present invention relates to a multiprocessor system, such as a super-computer, comprising a scalar unit for executing a scalar instruction and a vector unit for executing a vector instruction, and more specifically to an asymmetric vector multiprocessor capable of executing, using a single vector unit, vector instructions transmitted from a plurality of scalar units having different architectures.
2. Description of the Related Art
With recent high-performance data processing systems, a plurality of processors are provided in a data processing system, and an exclusive processor used exclusively to process operations and images is provided for a system. For example, a super-computer comprises a scalar processor for performing a scalar operation and a vector processor for performing a vector operation. When a vector operation instruction is detected by a scalar processor, the instruction is transmitted to the vector processor for execution.
A vector processor performs operations repeatedly at a high speed, and works especially efficiently in performing image processes, simulation, etc. where similar operations are repeatedly performed.
The vector processor has an architecture optimized for repeated operations represented, for example, by a DO loop in FORTRAN language, that is: ##EQU1##
A vector process refers to a process of repeatedly performing a given operation on a plurality of data. An operating unit for repeatedly performing operations is required to perform vector processes at a high speed.
A common microprocessing unit (MPU) executes a multiply instruction MUL 100 times when an instruction to repeat a multiplication 100 times is issued as described above. In this case, the instruction is fetched 100 times, the data are decoded 100 times, and operands are read and written 100 times respectively.
On the other hand, the vector processor performs a process using a single instruction as a series of operations of a register-specified number of repetitions (vector length) when a vector instruction such as multiply and other operation instructions, an input/output instruction, etc. is issued. Therefore, 99 fetching operations, decoding time, etc. can be successfully saved.
Accordingly, the vector processor performs a vector process to realize a highly efficient operations, thereby considerably reducing a total operation time.
Since the vector processor is provided with a plurality of operating units for executing in parallel a number of other instructions existing in the same loop and input/output instructions, higher efficiency can be realized in performing operations if, for example, an add instruction is added in a DO loop in FORTRAN language, that is, if operations represented as follows are to be repeatedly performed. ##EQU2##
In a super-computer, as described above, a vector instruction detected by a scalar processor (scalar unit) is transmitted to a vector processor (vector unit) for execution. In this case, a dual scalar processor (DSP) system has two scalar units connected to a single vector unit. FIG. 1 is the block diagram showing the configuration of the DSP system.
In FIG. 1, two scalar units 1 and 2 and a vector unit 3 are connected to a main storage device 4. Each of the scalar units 1 and 2 is connected to the vector unit 3. The DSP system executes vector instructions received from the two scalar units by a switching operation performed by a vector instruction executing unit in the vector unit. At this time, the architectures of the two scalar units connected to the vector unit have been limited to one type only.
Recently, various types of architectures have been developed. Among them, the architecture of a reduced instruction set computer (RISC) has made remarkable improvement in efficiency. However, in this case, a conventional operating system (OS) should be replaced with an OS for a new architecture in order to introduce the new architecture for a scalar unit of a super-computer provided with a scalar unit and a vector unit. If there is no OS for the new architecture, then an optional OS should be developed. Furthermore, if a new architecture is introduced, accumulated software resources for the conventional architecture cannot be utilized.
Since the architecture of a scalar unit is limited to only one type in the above described DSP system, there has been the problem that two different architectures cannot be used, that is, a conventional architecture for one scalar unit, and a new architecture for the other scalar unit.